View AK4526A_330740.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ASAHI KASEI
[AK4526A]
www..com
AK4526A
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION The AK4526A is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 20bit data and the DAC accepts up to 24bit input data. The ADC has an enhanced dual bit architecture with wide dynamic range. The DAC achieves low outband noise and high jitter tolerance by use of SCF(switched capacitor filter) techniques. An auxiliary digital audio input interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4526A has a dynamic range of 100dB and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC958(SPDIF) receiver such as the AK4110. The AK4526A is available in a small 44pin LQFP package which will reduce system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES * 2ch ADC with 20bit data output capability - 64x Oversampling - Sampling Rate up to 48kHz - Differential Inputs with single-ended use capability - S/(N+D): 92dB - Dynamic Range, S/N: 100dB - Digital HPF for offset cancellation - I/F format: MSB justified or I2S * 6ch DAC with 24bit data input capability - 128x Oversampling - Sampling Rate up to 96kHz - Single-Ended Outputs - 2nd order SCF - S/(N+D): 90dB - Dynamic Range: 100dB - S/N: 100dB, 108dB(Mute) - I/F format: MSB justified, LSB justified or I2S - Individual attenuation control with 21 levels and 1dB step * De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz * High Jitter Tolerance * TTL Level Digital I/F * Serial uP I/F for mode setting * Master clock: 256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=96kHz * Power Supply: 4.5 to 5.5V * Small 44pin LQFP
M0037-E-02 -1-
1999/6
ASAHI KASEI
[AK4526A]
n Block Diagram
www..com
MCKO
OCKS LIN+ LINRIN+ RIN-
ADC ADC
HPF HPF
Audio I/F
1/2
XTO XTI
Clock Gen
MCLK RX1 RX2 RX3 RX4 XTI XTO MCKO
MCLK LOUT1
VR
LPF
DAC
LRCK BICK LRCK BICK DAUX
DIR AK4110
LRCK BICK SDTO
ROUT1
VR
LPF
DAC
LOUT2
VR
LPF
DAC DEM
ROUT2
VR
LPF
DAC
SDOUT
DEM0 DEM1 DFS LRCK BICK SDIN SDOUT1 SDOUT2 SDOUT3
LOUT3
VR
LPF
DAC
SDIN1 SDIN2 SDIN3
SDOS SDTO
AC3
ROUT3
VR
LPF
DAC
SDTI1 SDTI2 SDTI3
AK4526A
Block Diagram (DIR and AC-3 DSP are external parts)
M0037-E-02 -2-
1999/6
ASAHI KASEI
[AK4526A]
n Ordering Guide
www..com
AK4526AVQ AKD4526A
-10 +70C 44pin LQFP (0.8mm pitch) Evaluation Board for AK4526A
n Pin Layout
CDTO/LOOP1 CDTI/LOOP0
CCLK/DIF1
CS /DIF0
XTO/MCKI
VREFH 35
41
38
43
42
39
37
44
40
AVSS
36
SDOS OCKS M/ S BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 17 22 Top View
34 33 32 31
VCOM
AVDD
P/ S
XTI
VREFL RIN+ RINLIN+ LINROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3
AK4526AVQ
30 29 28 27 26 25 24 23
MCKO
ICKS1
ICKS0
DVDD
DEM1
DEM0
DVSS
CAD1
M0037-E-02 -3-
CAD0
XTS
PD
1999/6
ASAHI KASEI
[AK4526A]
PIN/FUNCTION
www..com
No. 1
Pin Name SDOS
I/O I
Function SDTO Source Select Pin "L": Internal ADC output, "H": DAUX input ORed with serial control register if P/ S ="L". MCKO Clock Frequency Select Pin "L": MCLK, "H": MCLK/2 ORed with serial control register if P/ S ="L". Audio Data Master/Slave Mode Select Pin "L": Slave mode, "H": Master mode Audio Serial Data Clock Pin Input/Output Channel Clock Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Serial Data Output Pin AUX Audio Serial Data Input Pin Double Speed Sampling Mode Pin "L": Normal Speed, "H": Double Speed, the ADC is powered down. ORed with serial control register if P/ S ="L". De-emphasis Pin ORed with serial control register if P/ S ="L". De-emphasis Pin ORed with serial control register if P/ S ="L". Master Clock Output Pin Digital Power Supply Pin Digital Ground Pin Power-Down & Reset Pin When "L", the AK4526A is powered down and the control registers are reset to default state. If the state of P/ S , M/ S , CAD0-1 changes, then the AK4526A must be reset by PD . X'tal oscillator Select/Test Mode Pin "H": X'tal Oscillator selected "L": External clock source selected Input Clock Select 1 Pin Input Clock Select 0 Pin Chip Address Pin Used during the serial control mode. Chip Address Pin Used during the serial control mode. Lch #3 Analog Output Pin Rch #3 Analog Output Pin Lch #2 Analog Output Pin Rch #2 Analog Output Pin Lch #1 Analog Output Pin Rch #1 Analog Output Pin Lch Analog Negative Input Pin Lch Analog Positive Input Pin Rch Analog Negative Input Pin Rch Analog Positive Input Pin
2
OCKS
I
3 4 5 6 7 8 9 10 11
M/ S BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS
I I/O I/O I I I O I I
12 13 14 15 16
DEM1 DEM0 MCKO DVDD DVSS
I I O -
17
PD
I
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
XTS ICKS1 ICKS0 CAD1 CAD0 LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 LINLIN+ RINRIN+
I I I I I O O O O O O I I I I
M0037-E-02 -4-
1999/6
ASAHI KASEI
[AK4526A]
No. 34 35 36 37 38 39
Pin Name VCOM VREFH AVDD AVSS XTI XTO MCKI P/ S DIF0 CS DIF1 CCLK LOOP0 CDTI
33 VREFL www..com
I/O I O I I O I I I I I I I I I O
40 41 42 43
44
LOOP1 CDTO
Function Negative Voltage Reference Input Pin, AVSS Common Voltage Output Pin, AVDD/2 Large external capacitor is used to reduce power-supply noise. Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin Analog Ground Pin X'tal Input Pin X'tal Output Pin if XTS="H" External Master Clock Input Pin if XTS="L" Parallel/Serial Select Pin "L": Serial control mode, "H": Parallel control mode Audio Data Interface Format Pin in parallel mode Chip Select Pin in serial mode Audio Data Interface Format Pin in parallel mode Control Data Clock Pin in serial mode Loopback Mode Pin in parallel mode Enables digital loop-back from ADC to 3 DACs. Control Data Input Pin in serial mode Loopback Mode Pin in parallel mode Enables all 3 DAC channels to be input from SDTI1. Control Data Output Pin in serial mode
If pins XTS, ICKS0, ICKS1, PD , P/ S , DFS, DEM0, DEM1, CAD0, CAD1, M/ S , OCKS, SDOS are not driven, then XTS, ICKS0,ICKS1, CAD0, CAD1 must be tied to either AVSS or AVDD. PD , P/ S , DFS, DEM0, DEM1, M/ S , OCKS, SDOS must be tied to either DVSS or DVDD.
M0037-E-02 -5-
1999/6
ASAHI KASEI
[AK4526A]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1) www..com Parameter Power Supplies Analog Digital |AVSS-DVSS| (Note 2) Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Note:1. All voltages with respect to ground. 2. AVSS and DVSS must be same voltage level. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Symbol AVDD DVDD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 70 150 Units V V V mA V V C C
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 4.5 5.0 (Note 3) Digital DVDD 4.5 5.0
Note:1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical.
max 5.5 5.5
Units V V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
M0037-E-02 -6-
1999/6
ASAHI KASEI
[AK4526A]
ANALOG CHARACTERISTICS
www..com (Ta=25C; AVDD, DVDD=5V; AVSS, DVSS=0V; VREFH=AVDD, VREFL=AVSS; fs=44.1kHz;
Signal Frequency =1kHz; 20bit Data; Measurement Frequency=10Hz 20kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470 Resolution 20 Bits S/(N+D) (-0.5dB Input) (Note 4) 84 92 dB DR (-60dB Input, A-Weighted) 94 100 dB S/N (A-Weighted) (Note 5) 94 100 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/C Input Voltage AIN=0.6x(VREFH-VREFL) (Note 6) 2.85 3.0 3.15 Vpp Input Resistance 20 30 k Power Supply Rejection (Note 7) 50 dB DAC Analog Output Characteristics: Resolution 24 Bits S/(N+D) fs=44.1kHz 80 90 dB fs=96kHz 78 88 dB DR (-60dB Output, A-Weighted) fs=44.1kHz 95 100 dB fs=96kHz 94 100 dB S/N (A-Weighted) (Note 5) fs=44.1kHz 95 100 dB (Note 8) fs=96kHz 94 100 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Output Voltage AOUT=0.6x(VREFH-VREFL) 2.75 3.0 3.25 Vpp Load Resistance 5 k Power Supply Rejection (Note 7) 50 dB Output Volume Step Size Attenuation Control Range Power Supplies Power Supply Current (AVDD+DVDD) Normal Operation ( PD ="H") DFS="L" Power-down mode ( PD ="L") XTS="L" (Note 10) 1 2 mA (Note 9) 113 157 mA 0 -20 1 0 dB dB
Note: 4. In case of single ended input, S/(N+D)=83dB(typ, @AVDD=5V). 5. S/N measured by CCIR-ARM is 96dB at each converter and 94dB at ADC to DAC loopback. 6. Full scale input for each AIN+/- pin is 1.5Vpp in differential mode. 7. PSR is applied to AVDD, DVDD with 1kHz, 50mVpp. VREFH/VREFL pin is held a constant voltage. 8. DR and S/N at BW=40kHz are typically 93dB. 9. Typically, AVDD=90mA, DVDD=23mA. When DFS="H", AVDD=76mA and DVDD=22mA. 10. All digital input pins are held DVDD or DVSS. When XTS="H", typically 15mA.
M0037-E-02 -7-
1999/6
ASAHI KASEI
[AK4526A]
FILTER CHARACTERISTICS (fs=44.1kHz)
www..com (Ta=25C; AVDD, DVDD=4.5 5.5V; DEM=OFF)
Parameter ADC Digital Filter (Decimation LPF): Passband (Note 11) -0.005dB -0.02dB -0.06dB -6.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 12) Group Delay Distortion ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB -0.5dB -0.1dB DAC Digital Filter: Passband (Note 11) -0.06dB -6.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 12) DAC Digital Filter + Analog Filter: Frequency Response: 0 20.0kHz
Symbol PB
min 0 0 0 0 24.34 80
typ
max 19.76 20.02 20.20 22.05 0.005
Units kHz kHz kHz kHz kHz dB dB 1/fs us Hz Hz Hz
SB PR SA GD GD FR
29.3 0 0.9 2.7 6.0 0 0 24.1 43 14.7 0.2 20.0 22.05 0.06
PB SB PR SA GD FR
kHz kHz kHz dB dB 1/fs dB
Notes: 11. The passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz. 12. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 20bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal.
FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; AVDD, DVDD=4.5 5.5V; DEM=OFF) Parameter Symbol min typ DAC Digital Filter: Passband (Note 13) -0.06dB PB 0 -6.0dB 0 Stopband SB 52.5 Passband Ripple PR Stopband Attenuation SA 43 Group Delay (Note 12) GD 14.7 DAC Digital Filter + Analog Filter: FR Frequency Response: 0 20.0kHz 0.2 FR 40kHz -2
Note:13. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
max 43.5 48.0 0.06
Units kHz kHz kHz dB dB 1/fs dB dB
M0037-E-02 -8-
1999/6
ASAHI KASEI
[AK4526A]
DIGITAL CHARACTERISTICS
www..com (Ta=25C; AVDD, DVDD=4.5 5.5V)
Parameter High-Level Input Voltage (XTS pin) (All pins except XTS pin) Low-Level Input Voltage (XTS pin) (All pins except XTS pin) Hight-Level Output Voltage (Iout= -1mA) Low-Level Output Voltage (Iout= 1mA) Input Leakage Current
Symbol VIH1 VIH2 VIL1 VIL2 VOH VOL Iin
min 90%DVDD 2.2 DVDD-0.4 -
typ -
max 10%DVDD 0.8 0.4 10
Units V V V V V V uA
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.5 5.5V; CL=20pF) Parameter Symbol min fCLK 8.192 Master Clock Input 256fs: Pulse Width Low tCLKL 27 Pulse Width High tCLKH 27 384fs: fCLK 12.288 Pulse Width Low tCLKL 20 Pulse Width High tCLKH 20 512fs: fCLK 16.384 Pulse Width Low tCLKL 15 Pulse Width High tCLKH 15 Frequency fMCK 4.096 MCKO Output Duty (XTS="H") dMCK 40 LRCK frequency DAC Normal Speed Mode (DFS="0") fsn 32 DAC Double Speed Mode (DFS="1") fsd 64 Duty Cycle Duty 45 Audio Interface Timing Slave mode tBCK 160 BICK Period tBCKL 65 BICK Pulse Width Low tBCKH 65 Pulse Width High tLRB 45 LRCK Edge to BICK "" (Note 14) tBLR 45 BICK "" to LRCK Edge (Note 14) tLRS LRCK to SDTO(MSB) tBSD BICK "" to SDTO tSDH 40 SDTI Hold Time tSDS 25 SDTI Setup Time
Master mode BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO SDTI Hold Time SDTI Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS
typ
max 12.288
18.432
24.576
50
24.576 60 48 96 55
Units MHz ns ns MHz ns ns MHz ns ns MHz % kHz kHz %
40 50
ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns
64fs 50 -20 40 25 20 50
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
M0037-E-02 -9-
1999/6
ASAHI KASEI
[AK4526A]
Parameter
www..com Timing Control Interface
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tR1 tF1 tR2 tF2 (Note 15) (Note 16) tPD tPDV
min 200 80 80 40 40 150 50 50
typ
max
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1/fs
CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CS "H" Time CS "" to CCLK "" CCLK "" to PD "" CCLK "" to CDTO valid CS "" to CDTO Hi-Z Rise Time of CS Fall Time of CS Rise Time of CCLK Fall Time of CCLK Reset Timing PD Pulse Width PD "" to SDTO valid
45 70 20 20 20 20 150 516
Note:15. The AK4526A can be reset by bringing PD "L" to "H" only upon power-up. When X'tal mode(XTS="H"), at power-up, PD should be held "L" for 5ms to allow the X'tal oscillation to begin. 16. These cycles are the number of LRCK rising from PD rising.
n Timing Diagram
1/fCLK VIH2 VIL2 tCLKH tCLKL
MCKI/XTI
1/fs VIH2 VIL2
LRCK
tBCK VIH2 VIL2 tBCKH tBCKL
BICK
Clock Timing
M0037-E-02 - 10 -
1999/6
ASAHI KASEI
[AK4526A]
www..com
LRCK tBLR tLRB
VIH2 VIL2
BICK
VIH2 VIL2 tLRS tBSD VIH2 VIL2 tSDS tSDH VIH2 VIL2
SDTO
SDTI
Audio Interface Timing (Slave mode)
VIH2 VIL2 tMBLR BICK VIH2 VIL2 tBSD VIH2 VIL2 tSDS tSDH VIH2 VIL2
LRCK
SDTO
SDTI
Audio Interface Timing (Master mode)
VIH2 CS VIL2 tCSS tCCKL tCCKH VIH2 VIL2 tCDS tCDH VIH2 VIL2
CCLK
CDTI
C1
C0
R/W
A4
CDTO
Hi-Z
WRITE/READ Command Input Timing
M0037-E-02 - 11 -
1999/6
ASAHI KASEI
[AK4526A]
tCSW
www..com
CS
VIH2 VIL2 tCSH CCLK VIH2 VIL2
CDTI
D3
D2
D1
D0
VIH2 VIL2
CDTO
Hi-Z
WRITE Data Input Timing
tCSW VIH2 CS
tCSH CCLK
VIH2 A1 A0 VIL2 tDCD Hi-Z CDTO D7 D6 D5 VIH2 VIL2
tCSW VIH2 CS VIL2 tCSH CCLK VIH2 VIL2
CDTI
VIH2 VIL2 tCCZ
CDTO
D3
D2
D1
D0
VIH2 VIL2
READ Data Output Timing 2
tPDW
PD
VIL2
Power Down & Reset Timing
M0037-E-02 - 12 -
1999/6
ASAHI KASEI
[AK4526A]
OPERATION OVERVIEW
www..com
n System Clock
The master clock can be either a crystal resonator placed across the XTI and XTO pin (XTS="H"), or external TTL level clock input to the MCKI pin (XTS="L") with the XTI pin left floating. The relationship between the master clock and the desired sample rate is defined in Table 1. The sampling rate corresponds to 32kHz 48kHz at normal speed mode (DFS="0") and 64kHz 96kHz (DFS="1"). The LRCK clock input must be derived from the master clock, and the phase is not critical. Either the same or a half frequency of XTI/MCKI frequency for the master clock output (MCKO) can be selected by OCKS. MCKO may be used as the master clock for the additional ADC or DAC. The ADC is powered down during double speed mode (DFS="1"). In slave mode, MCKI should be synchronized with LRCK but the phase is not critical. External clocks (MCKI, BICK) should always be present whenever the AK4526A is in normal operation mode ( PD ="H"). If these clocks are not provided, the AK4526A may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4526A should be in the power-down mode ( PD ="L"). After exiting reset at power-up etc., the AK4526A is in the power-down mode until MCKI and LRCK are input.
No. 0 1 2 3
ICKS1 0 0 1 1
ICKS0 0 1 0 1
XTI/MCKI DFS="0" DFS="1" 256fs 128fs 384fs 192fs 512fs 256fs 256fs 256fs
at reset
Table 1. Master clock frequency select
When changing DFS, some click noise may occur. At that case, the analog outputs should be muted externally or by the internal attenuators.
min. 5/fs
DFS
MUTE
min. 0s
Figure 1. External mute timing at DFS change
When using crystal oscillator, external loading capacitor ( 40pF to AVSS for XTI/XTO) are required. When X'tal mode (XTS="H"), at power-up, PD should be held "L" for 5ms to allow the X'tal oscillation to begin.
AK4526A
XTI
XTO
Figure 2. X'tal resonator connection (XTS="H") M0037-E-02 - 13 1999/6
ASAHI KASEI
[AK4526A]
n De-emphasis Filter
www..com
The AK4526A includes the digital de-emphasis filter (tc=50/15us) by IIR filter. This filter corresponds to four sampling frequencies (32kHz, 44.1kHz, 48kHz, 96kHz). In parallel control mode (P/ S ="H"), de-emphasis mode is selected by the DFS, DEM1 & DEM0 pins. In serial control mode (P/ S ="L"), de-emphasis is set by OR of pins and register. No. 0 1 2 3 4 5 6 7 DFS 0 0 0 0 1 1 1 1 DEM1 0 0 1 1 0 0 1 1 DEM0 0 1 0 1 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz OFF OFF 96kHz OFF at reset
Table 2. De-emphasis control
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and also scales with sampling rate (fs).
n Analog Volume Control
The DAC outputs include analog volume and may be independently attenuated in 1dB steps. Level changes attenuate the DAC and the internal filter noise with the signal until the residual noise floor is equal to the noise floor of the output buffer. Level changes only occur during zero-crossings to minimize audible artifacts. If these is no zero-crossings, then the level will change after a time-out. The time-out period scales with fs. The periods of 256/fs, 512/fs, 1024/fs and 2048/fs are selectable by TM1-0 bits. For each DAC channel, there is a register status bit that indicates if the level change has occurred. If the attenuation register is written to before the status flag is cleared , the previous level change is made and the timer is reset. Zero-crossing detection may be disabled by serial control. The on-chip volume can attenuate the DAC output from 0dB to -20dB. Table 3 shows the S/N of the DAC at each attenuation level. Output Volume Setting -10dB 96dB 92dB
0dB A-weight CCIR-ARM 100dB 96dB
-20dB 88dB 84dB
Table 3. DAC S/N
M0037-E-02 - 14 -
1999/6
ASAHI KASEI
[AK4526A]
n Audio Serial Interface Format
www..com
The audio interface corresponds to both master mode and slave mode. LRCK and BICK are inputs in slave mode. For master mode, LRCK outputs fs clock and BICK outputs 64fs clock. Four serial data modes can be selected by the DIF0 and DIF1 pins as shown in Table 4. In all modes the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the rising edge of BICK. Figure 3-5 shows the timing at SDOS="L". In this case, the SDTO outputs the ADC output data. When SDOS="H", the data input to DAUX is converted to SDTO's format and output from SDTO. Mode 2 and mode 3 in SDTI/DAUX input formats can be used for 16-20bit data by zeroing the unused LSBs. SDTO ADC DAUX SDOS="L" SDOS="H" 20bit, MSB justified 20bit, MSB justified 20bit, MSB justified 24bit, MSB justified 20bit, MSB justified 24bit, MSB justified 20bit, IIS (I2S) 24bit, IIS (I2S) Table 4. Audio data formats SDTI, SDTI2, SDTI3, DAUX 20bit, LSB justified 24bit, LSB justified 24bit, MSB justified 24bit, IIS (I2S)
Mode 0 1 2 3
DIF1 0 0 1 1
DIF0 0 1 0 1
LRCK H/L H/L H/L L/H
LRCK
0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 8 7 6 0 19 18 8 7 6 0 19
Don't Care 19:MSB, 0:LSB
19 18
12 11
1
0
Don't Care
19 18
12 11
1
0
Lch Data
Rch Data
Figure 3. Mode 0 Timing
LRCK
0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 12 11 10 0 19 18 12 11 10 0 19
Don't Care
23 22
12 11
1
0
Don't Care
23 22
12 11
1
0
SDTO-19:MSB, 0:LSB; SDTI-23:MSB, 0:LSB Lch Data
Rch Data
Figure 4. Mode 1 Timing *When SDOS="H", up to 24bit data is output from SDTO.
M0037-E-02 - 15 -
1999/6
ASAHI KASEI
[AK4526A]
LRCK
www..com0
1 2 18 19 20 21 22 23 24 25 0 1 2 18 19 20 21 22 23 24 25 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 1 0 19 18 1 0 19
23 22
5
4
3
2
1
0
Don't Care 23 22
5
4
3
2
1
0 Don't Care 23
SDTO-19:MSB, 0:LSB; SDTI-23:MSB, 0:LSB Lch Data
Rch Data
Figure 5. Mode 2 Timing *When SDOS="H", up to 24bit data is output from SDTO. LRCK
0 1 2 3 19 20 21 22 23 24 25 0 1 2 18 19 20 21 22 23 24 25 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 1 0 19 18 1 0 0 Don't Care
23 22
5
4
3
2
1
0
Don't Care 23 22
5
4
3
2
1
SDTO-19:MSB, 0:LSB; SDTI-23:MSB, 0:LSB Lch Data
Rch Data
Figure 6. Mode 3 Timing *When SDOS="H", up to 24 bit data is output from SDTO.
M0037-E-02 - 16 -
1999/6
ASAHI KASEI
[AK4526A]
n Power-Down & Reset
www..com
The ADCs and DACs of AK4526A are placed in the power-down mode by bringing PD "L" and both digital filters are reset at the same time. PD "L" also reset the control registers to their default values. This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 7 shows the power-up sequence.
PD
516/fs
(1)
ADC Internal State DAC Internal State
Normal Operation
Power-down
Init Cycle
Normal Operation
Normal Operation GD (2)
Power-down
Normal Operation GD
ADC In (Analog) ADC Out (Digital) DAC In (Digital)
(2) GD (3) "0"data (4)
"0"data GD (5) (5)
DAC Out (Analog) Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
External Mute
(6)
Mute ON
(1) The analog part of ADC is initialized after exiting the power-down state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) A/D output is "0" data at the power-down state. (4) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. Required muting time depends on the configuration of the input buffer circuits. Figure 10: 1s Figure 11: 200ms (5) Click noise occurs at the edge of PD . (6) Please mute the analog output externally if the click noise (5) influences system application. Figure 7. Power-up sequence During the power-down mode, the crystal oscillator is left running if XTS="H". The condition of the outputs are as follows. CDTO = high impedance SDTO = "L" MCKO = Clock out LRCK = "L" (master mode) BICK = "L" (master mode) AOUT = VCOM (AVDD/2)
M0037-E-02 - 17 -
1999/6
ASAHI KASEI
[AK4526A]
n Mode Control Interface
www..com
Control may be configured directly by pins during the parallel control mode. The serial control interface is enabled by the P/ S pin = "L". In this mode, internal registers may be either written to or read by the 4 wire uP interface pins: CS , CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C0/1) Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CS . For read operations, the CDTO output goes high impedance after a low-to-high transition of CS . The operation of the control serial port may be completely asynchronous with the audio sample rate. The chip address is determined by the state of the CAD0 and CAD1 inputs. PD = "L" resets the registers to their default values.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI CDTO CDTI READ CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
Hi-Z
C0 C1 R/W A4 A3 A2 A1 A0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1-C0: R/W A4-A0: D7-D0:
Chip Address (4 address selectable) READ/WRITE (0:READ, 1:WRITE) Register Address Control data Figure 8. Control I/F Timing
M0037-E-02 - 18 -
1999/6
ASAHI KASEI
[AK4526A]
n Register Map
www..com
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H
Register Name Control 1 Control 2 LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control Volume Status
D7 0 0 0 0 0 0 0 0 0
D6 TM1 0 0 0 0 0 0 0 0
D5
D4
D3 DIF1 SDOS ATT3
ATT3
D2 DIF0 DFS ATT2
ATT2
D1 OCKS
DEM1
D0 MUTE DEM0 ATT0
ATT0
TM0 ZCD LOOP1 LOOP0 0 ATT4
0 ATT4
ATT1
ATT1
0 0 0 0 R3
ATT4 ATT4 ATT4 ATT4 L3
ATT3 ATT3 ATT3 ATT3 R2
ATT2 ATT2 ATT2 ATT2 L2
ATT1 ATT1 ATT1 ATT1 R1
ATT0 ATT0 ATT0 ATT0 L1
Note: For addresses from 09H to 1FH, data is not written and only "0" is read back. PD = "L", resets the registers to their default values.
n Register Definitions
Addr 00H Register Name Control 1 R/W RESET D7 0 R 0 D6 TM1 R/W 1 D5 TM0 R/W 0 D4 ZCD R/W 0 D3 DIF1 R/W 0 D2 DIF0 R/W 0 D1 OCKS R/W 0 D0 MUTE R/W 0
MUTE: DAC mute control 0: Normal operation 1: DAC outputs muted MUTE causes all DAC outputs to be muted. The registers of each volume setting are preserved during mute and the DAC outputs return to their previous volume setting after MUTE is programmed "L". Muting is done according to the ZCD, TM1 and TM0 register settings. OCKS: Output Clock Frequency Select 0: MCKO = master clock 1: MCKO = master clock / 2 Register bit is ORed with OCKS pin if P/ S = "L". DIF1-0: Audio data interface modes (see Table 4) 00: Mode 0 01: Mode 1 10: Mode 2 11: Mode 3 ZCD: Zero crossing disable 0: DAC attenuation changes occur only on zero-crossing or after timeout. 1: DAC attenuation changes occur immediately. TM1-0: Zero crossing time out period select 00: 256/fs 01: 512/fs 10: 1024/fs 11: 2048/fs
M0037-E-02 - 19 -
1999/6
ASAHI KASEI
[AK4526A]
Addr Register Name www..com 01H Control 2 R/W RESET
D7 0 R 0
D6 0 R 0
D5 R/W 0
D4 R/W 0
D3 SDOS R/W 0
D2 DFS R/W 0
D1
DEM1
D0 DEM0 R/W 0
LOOP1 LOOP0
R/W 0
DFS, DEM1-0: De-emphasis response 000: 44.1kHz 001: OFF 010: 48kHz 011: 32kHz 100: OFF 101: OFF 110: 96kHz 111: OFF Register bits are ORed with DFS, DEM1, DEM0 pins if P/ S = "L". ADC is poewered down at DFS = "1".
SDOS: SDTO source select 0: ADC SDTO 1: DAUX/De-emphasis SDTO Register bit is ORed with SDOS pin if P/ S = "L". LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN LOUT1, LOUT2, LOUT3 RIN ROUT1, ROUT2, ROUT3 The digital ADC output is connected to the digital DAC input. In this mode, SDTO is output by SDOS and the input DAC data to SDTI1-3 is ignored. In 96kHz mode the ADC output to DAC input goes to all "0". 10 SDTI1(L) SDTI2(L), SDTI3(L) SDTI1(R) SDTI2(R), SDTI3(R) In this mode the input DAC data SDTI2 and SDTI3 is ignored. 11: N/A When the audio format is set mode 1 at loopback mode, the audio format of SDTO becomes mode 3.
M0037-E-02 - 20 -
1999/6
ASAHI KASEI
[AK4526A]
Addr Register Name www..com 02H 03H 04H 05H 06H 07H
LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control
D7 0 0 0 0 0 0 R 0
D6 0 0 0 0 0 0 R 0
D5 0 0 0 0 0 0 R 0
D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 R/W 0
D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 R/W 0
D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 R/W 0
D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 R/W 0
D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 R/W 0
R/W RESET ATT4-0: Attenuation level 00000: 0dB 00001: -1dB 00010: -2dB 10011: -19dB 10100: -20dB 10101: Mute 10111: Mute
Addr 08H
Register Name Volume Status R/W RESET
D7 0 R 0
D6 0 R 0
D5
R3
D4
L3
D3
R2
D2
L2
D1
R1
D0
L1
R 0
R 0
R 0
R 0
R 0
R 0
L3-1, R3-1: Attenuation change status 0: Attenuation level changed 1: Waiting for zero-crossing or timeout
M0037-E-02 - 21 -
1999/6
ASAHI KASEI
[AK4526A]
SYSTEM DESIGN
www..com
Figure 9 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
Analog 5V
+ 10k uP +10u 0.1u 0.1u CDTO 44 CDTI 43 CCLK 42 CS 41 P/ S 40 MCKI 39 XTI 38 AVSS 37 AVDD 36 VREFH 35 Digital Audio Source (DIR) 1 SDOS 2 OCKS 3 M/ S 4 BICK 5 LRCK Audio DSP (MPEG/ AC3) 6 SDTI1 7 SDTI2 8 SDTI3 9 SDTO 10 DAUX 11 DFS 14 MCKO 19 ICKS1 20 ICKS0 15 DVDD 13 DEM0 12 DEM1 16 DVSS 21 CAD1 18 XTS 17 PD Mode Setting (DVDD or DVSS) VCOM 34 VREFL 33 330 RIN+ 32 1.5n RIN- 31 330 LIN+ 30 10u
AK4526A
1.5n LIN- 29 330 ROUT1 28 LOUT1 27 ROUT2 26 LOUT2 25 ROUT3 24 LOUT3 23 22 CAD0
0.1u 10u + 5
Mode Setting (AVDD or AVSS)
Power on reset System Ground Digital Ground
Analog Ground
Figure 9. Typical Connection Diagram
If pins XTS, ICKS0, ICKS1, PD , P/ S , DFS, DEM0, DEM1, CAD0, CAD1, M/ S , OCKS, SDOS are not driven, then XTS, ICKS0, ICKS1, CAD0, CAD1 MUST BE tied either AVSS or AVDD. PD , P/ S , DFS, DEM0, DEM1, M/ S , OCKS, SDOS must be tied either DVSS or DVDD.
M0037-E-02 - 22 -
1999/6
ASAHI KASEI
[AK4526A]
1. Grounding and Power Supply Decoupling
www..com
The AK4526A requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4526A should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4526A as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The differential voltage between VREFH and VREFL sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1uF ceramic capacitor and VREFL pin is connected to AVSS. VCOM is a signal ground of this chip. An electrolytic capacitor 10uF parallel with a 0.1uF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted coupling into the AK4526A.
3. Analog Inputs
The ADC inputs are differential and internally biased to the common voltage (AVDD/2) with 30k (typ) resistance. Figure 10 is a circuit example which analog signal is input by single end. The signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x (VREFH-VREFL) Vpp. In case of single ended input, the distortion around full scale degrades compared with differential input. Figure 11 is a circuit example which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x (VREFH-VREFL) Vpp. The AK4526A can accept input voltages from AVSS to AVDD. The ADC output data format is 2's complement. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a negative fill scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the internal HPF. The AK4526A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs.
AK4526A
RIN+ 32 0.1nF + RIN- 31 2.2nF LIN+ 30 0.1nF + LIN- 29 4.7nF 4.7nF 10u Signal 3.0Vpp 2.2nF 470 10u Signal 3.0Vpp
470
Figure 10. Single End Input Example
M0037-E-02 - 23 -
1999/6
ASAHI KASEI
[AK4526A]
www..com
4.7k 1.5Vpp 10k 330 330 RIN- 31 1.5Vpp LIN+ 30 LIN- 29 4.7k Vop=AVDD=5V 4.7k Same circuit 0.1u BIAS + 10u + NJM2100 10k Vop + 10k Vop 22u Signal 3.2Vpp
AK4526A
RIN+ 32
1.5nF
Figure 11. Differential Input Buffer Example
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x (VREFH-VREFL) Vpp. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
M0037-E-02 - 24 -
1999/6
ASAHI KASEI
[AK4526A]
n Layout Example
www..com
Figure 12 shows a layout example in the following condition. External clock mode, Slave mode and Serial control mode with Address "00".
Analog 5V
+ 10u
uP
+10u 0.1u 0.1u CDTO 44 CDTI 43 CCLK 42 CS 41 P/ S 40 MCKI 39 XTI 38 AVSS 37 AVDD 36 VREFH 35 21 CAD1 VCOM 34 VREFL 33 RIN+ 32 RIN- 31 LIN+ 30 LIN- 29 ROUT1 28 LOUT1 27 ROUT2 26 LOUT2 25 ROUT3 24 LOUT3 23 14 MCKO 19 ICKS1 20 ICKS0 15 DVDD 12 DEM1 13 DEM0 16 DVSS 22 CAD0 18 XTS 5 17 PD
DIR 1 SDOS 2 OCKS 3 M/ S 4 BICK 5 LRCK DSP 6 SDTI1 7 SDTI2 8 SDTI3 9 SDTO 10 DAUX 11 DFS
AK4526A Top View
0.1u 10u + Power on reset
System Ground
Digital Ground
Analog Ground
Figure 12. Layout example
M0037-E-02 - 25 -
1999/6
ASAHI KASEI
[AK4526A]
n Peripheral I/F Example
www..com
The AK4526A can accept the signal of device with a nominal 3.3V supply because of TTL input. However as the digital output level is 5V, the peripheral device must accept 5V signal when the device operate at a nominal 3.3V supply. Figure 13 shows an example with the mixed system of 3.3V and 5V.
3.3V Analog Audio signal PLL I/F DSP 3.3V Digital
AK4110 5V Analog 5V Digital
Analog Digital Control signal AK4526A
uP & Others
Figure 13. Power supply connection example
M0037-E-02 - 26 -
1999/6
ASAHI KASEI
[AK4526A]
n Applications
www..com
1) Zoran AC3 decoder, ZR38500
SDTO SDTI1 AK4526A SDTI2 SDTI3 LRCK BICK MCLK 256fs 256fs MCKO1 AK4110 Digital Input RX LRCK BICK SDTO ZR38500 SDA SDB SDC SDD WSB SCKB
Analog Input Analog Output
WSA SCKA SDE
2) Zoran AC3 decoder, ZR38600
SDTO SDTI1 Analog Input AK4526A SDTI2 SDTI3 Analog Output DFS LRCK BICK XTI SDA SDB SDC SDD WSB SCKB ZR38600 WSA SCKA SCKIN GPIO2 Digital Input SPFRX
3) Yamaha AC3 decoder, YSS912
SDTO SDTI1 AK4526A SDTI2 SDTI3 LRCK BICK MCLK 256fs 256fs MCKO1 LRCK YM3436 BICK or AK4110 SDTO RX YSS912 SDIA1 SDOB0 SDOB1 SDOB2 SDWCK0 SDBCK0
Analog Input Analog Output
Digital Input
SDIA0
M0037-E-02 - 27 -
1999/6
ASAHI KASEI
[AK4526A]
PACKAGE
www..com
44pin LQFP (Unit: mm)
12.800.30 1.70max 00.2 10.00 33 34 23
22 12.800.30 10.00 12
0.80 44 1 0.370.10 11
0.170.05 010
0.600.20 | 0.15
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
M0037-E-02 - 28 -
1999/6
ASAHI KASEI
[AK4526A]
MARKING
www..com
AKM
AK4526AVQ XXXXXXX JAPAN
1
1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4526AVQ 4) Country of Origin 5) Asahi Kasei Logo
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
M0037-E-02 - 29 -
1999/6

▲Up To Search▲

Price & Availability of AK4526A

	To Download AK4526A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .